Communication systems typically utilize some form of clock system to synchronize communications between a transmitter and a receiver. In digital communication systems the receiver must operate at the same average frequency as the transmitting end to prevent loss of information. When digital signals are transported over a network of digital communication links, switching nodes, multiplexers, transmission line interfaces, and the task of keeping all the entities operating at the same average frequency is referred to as network synchronization.
Generally, in Gigahertz communication systems it is important that a receiver reads or samples the data waveform when the amplitude of the data waveform reaches a steady state. Many techniques can be utilized to determine when to sample the data waveform and this process is commonly referred to as clock and data recovery (CDR). In a CDR system, when the timing of the receiver is synchronized with the data waveform, a sampling clock of the receiver will trigger a receiving component such as a latch to acquire the logic value provided by the waveform at an appropriate time. Traditional CDR systems utilize two system clocks or two sampling clock signals that cycle every bit interval or bit cycle and thus consume considerable power. A first monitoring clock is typically utilized to detect the timing of the incoming waveform and the first clock can control or synchronize a second clock that actually controls when the data waveform is sampled for data acquisition.
CDR systems generally operate plesiochronously where a transmitter clock has a frequency that operates at a “known” frequency and the receiver clock operates at the same frequency, with some small frequency offset. Plesiochronous operation occurs generally where critical timing moments occur nominally at the same rate and any variation in rate is constrained within specified limits. Although the frequency of the sampling clock can be set based on the frequency of the transmitter clock, unknown delays can occur between the transmitter and the receiver. In addition, the timing of the received waveform can undergo random changes, known as timing jitter, which are induced by non-idealities of the clock circuitries. Hence, the exact sample time needs to be determined by the receiver in order to accurately recover data from the transmitted data waveform.
Ideally, clock and data recovery circuitry can perform voltage detection and “phase slicing” levels in relation to a center of a pulse or a position between subsequent transitions of a differential signal. A differential signal has two signals that are one hundred eighty degrees out of phase and each signal can be carried on a separate conductor. These signals are often labeled as a data signal and a complementary data signal. Since the signals are 180 degrees out of phase, when data is being transmitted, the signal on the data line will have an opposite value of the signal on the complementary data line. It can be appreciated that signals cannot transition instantaneously and particularly in high speed Gigahertz communications signals the time interval that the signal stays at is steady state may be shorter than the time required for the signal to transition, and thus, when certain bit patterns are present, the data waveform can look like a sin wave. Accordingly, a picture of a differential signal often looks like two opposing sinusoidal waves that crossover at an average voltage on the graph at various intervals depending on the content of the data being transmitted.
Thus, between crossovers of differential data signals or waveforms an eye shape is typically formed, often called an eye pattern. Since the differential signal can “float” with reference to ground and the voltages and differential voltage can continually change, often, the size of the eye will continually change or be stressed, however some form of an eye pattern will typically remain. In many applications, the preferred time to read the data is in the middle of the eye or half way between where the differential signals cross over each other during consecutive transitions. However, it is often difficult to determine an optimum time to sample the data waveform because for example, the optimum time may not be at the center of the eye pattern due to waveform anomalies.
Recent advances in CDR systems have implemented additional circuits that can determine the center of the eye of the waveform, and/or a preferred time to sample the data stream. As stated above, virtually all of these designs have multiple system clocks and other control circuitry and such systems draw a significant amount of power and take up a lot of valuable space on an integrated circuit. Although some of these configurations do improve the bit error rates, the penalty paid in power and size far outweighs the benefits provided by such circuits.
As stated above, many CDR systems synchronize to the incoming data waveform by detecting a crossover of the two differential data lines and then sample the data waveform responsive to a sampling clock signal that triggers a read of the data waveform half way into the bit cycle. Thus, data is acquired from the transmission line during a distinct time interval when the sampling clock is active. Clock generation and distribution circuits are one of, if not the biggest power consumers in an integrated circuit. More particularly, clock circuits utilized in data receiving circuits are very “power hungry” because multiple clocks are required. These multiple clocks must be accurate and are therefore generated by complex “power hungry” phase generator circuits. These circuits include delay-locked-loop (DLL), phase-locked loop (PLL), and phase rotator type clock generator circuits.
Currently, communication or information systems are transmitting and receiving data in the Gigabit per second range. Increasing the accuracy of CDR amidst noise and distortions often present on a transmission line is a formidable task because the time intervals of signal transitions and steady state values can become very small and this requires extreme precision of the clock signals. As stated above, clock generation and distribution in CDR circuits is one of the biggest contributors to power consumption. Thus, an architecture with minimal clock signals and minimal clock signal transitions will provide a significant improvement in CDR systems.